Integrated circuits are made up of millions of active devices formed in or on silicon substrates. The active devices are interconnected to form functional circuits and components. The devices are interconnected through the use of well-known multilevel interconnections. Interconnection structures normally have a first layer of metallization, an interconnection layer, a second level of metallization, and sometimes a third or other subsequent levels of metallization. Interlevel dielectrics, such as doped and undoped silicon dioxide (SiO2) or low-K dielectric materials, are used to electrically isolate the different levels of metallization in a silicon substrate or well. The electrical connections between different interconnection levels are made through the use of metallized vias. U.S. Pat. No. 4,789,648, which is incorporated herein by reference, describes a method for preparing multiple metallized layers and metallized vias in insulating films. Metallization layers are also used to form electrical interconnections on the same layer of a semiconductor device. Additionally, metal contacts are used to form electrical connections between interconnection levels and devices formed in wells. Metal vias and contacts may be filled with various metals and alloys including titanium (Ti), titanium nitride (TiN), tantalum (Ta), aluminum copper (Al—Cu), aluminum silicon (Al—Si), copper (Cu), tungsten (W), and combinations thereof.
In one conventional semiconductor manufacturing process, metallized vias or contacts are formed by a blanket metal deposition followed by a chemical mechanical polish (CMP) step. In one example process, via holes are etched through an interlevel dielectric (ILD) to interconnection lines or to a semiconductor substrate. Next, a thin adhesion layer such as tantalum nitride and/or tantalum is generally formed over the ILD and is directed into the etched via hole. Then, a metal film is blanket deposited over the adhesion layer and into the via hole. Deposition is continued until the via hole is filled with the blanket deposited metal. Finally, the excess metal is removed by chemical mechanical polishing (CMP) to form metal vias.
In a typical chemical mechanical polishing process, the substrate is placed in direct contact with a rotating polishing pad. Pressure is applied to maintain pressure against the backside of the substrate. During the polishing process, the pad and substrate are rotated with respect to each other while pressure is maintained between the substrate and pad. An abrasive and chemically reactive solution, commonly referred to as a “slurry”, is applied to the pad during polishing. The slurry initiates the polishing process by abrading and chemically reacting with the film being polished. The polishing process is facilitated by the rotational movement of the pad relative to the substrate while a slurry is provided at the wafer/pad interface. Polishing continues in this manner until the desired film on the insulator is removed. The slurry composition is an important factor in the CMP step. Depending on the choice of the oxidizing agent, the abrasive, as well as certain other additives, the polishing slurry can be tailored to provide effective polishing to metal layers at desired polishing rates while minimizing surface imperfections, defects and corrosion and erosion.
Typically CMP polishing slurries contain abrasive materials, such as silica or alumina, suspended in an oxidizing, aqueous medium. For example, slurries containing alumina, hydrogen peroxide, and either potassium or ammonium hydroxide are useful for removing tungsten at predictable rates with little removal of the underlying insulating layer. Many other slurry compositions are used to react and selectively abrade the surface of a substrate.
In another approach, used for CMP of copper metallization layers, abrasives are suspended in an ethylene glycol mixture that contains a phosphoric acid (H3PO4) oxidizer. Although generally suitable, such a slurry suffers from a number of drawbacks. CMP with such a slurry results in excessive dishing in wider copper regions. In general, such a process also induces erosion of copper interconnect structures and damages low-K films on semiconductor wafers. Such a process can also leave isolated copper “islands” that can cause metal line bridging and shorting. Most importantly, CMP with such slurries is not effective at removing smaller sub-micron surface defects.
Although certain of these conventional CMP processes and slurries have proven useful, improvements can be made. Desirable surface polishing processes and materials exhibit good thin film polishing selectivity and simultaneously give polished substrates with minimal dishing, low defectivity, and low incidence of isolated metal “islands” on the polished surfaces. In particular, a method is needed for polishing copper-containing metallization layers with good thin film polishing selectivities and simultaneously achieve minimal dishing and low defectivity in the copper-containing layers. For these and other reasons, improved polishing methods and materials are needed.